Adlink PCIe-7300A Bedienungsanleitung

Advance Technologies; Automate the World.Manual Rev. 2.50Revision Date: July 1, 2008Part No: 50-11106-1030PCI/PCIe/cPCI-7300A80 MB Ultra-High Speed

vi List of Figures

90 C/C++ LibrariesBufNotDWordAlignDMADscrBadAlign

C/C++ Libraries 915.22 _7300_DO_PG_Stop@ Description This function is used to stop the pattern generation operation. After executing this function,

92 C/C++ Libraries5.23 _7300_DI_Timer@ Description This function is used to set the internal timer pacer for digital input. Timer pacer frequency = 1

C/C++ Libraries 935.24 _7300_DO_Timer@ Description This function is used to set the internal timer pacer for digital out-put. Timer pacer frequency

94 C/C++ Libraries5.25 _7300_Int_Timer@ Description This function is used to set Counter #2.@ SyntaxVisual C/C++ (Windows 95)int W_7300_Int_Timer (in

C/C++ Libraries 955.26 _7300_Get_Sample@ Description For the language without pointer support such as Visual Basic, programmer can use this function

96 C/C++ Libraries5.27 _7300_Set_Sample@ Description For the language without pointer support such as Visual Basic, programmer can use this function

C/C++ Libraries 975.28 _7300_GetUnderrunStatus@ Description When you use _7300_DO_DMA_Start to output data, the output data is read from the FIFO on

98 C/C++ Libraries

Appendix 99Appendix8254 Programmable Interval TimerNote: The material of this section is adopted from “Intel Micropro-cessor and Peripheral Handbook

Introduction 11 IntroductionThe cPCI/PCI/PCIe-7300A is cPCI/PCI/PCI Express form factor ultra-high speed digital I/O card, it consists of 32 digital

100 AppendixControl Byte: (Base + 7, Base + 11)X SC1 & SC1 - Select Counter (Bit7 & Bit 6)X RL1 & RL0 - Select Read/Load operation (Bit 5

Appendix 101 2. The count of the BCD counter is from 0 up to 99,999.Mode DefinitionIn 8254, there are six different operating modes can be selec

102 AppendixThe gate input when low, will force the output high. When the gate input goes high, the counter will start form the initial count. Thus,

Appendix 103Mode 5: Hardware Triggered Strobe.The counter will start counting after the rising edge of the trig-ger input and will go low for one clo

104 Appendix

2 Introduction1.1 ApplicationsX Interface to high-speed peripheralsX High-speed data transfers from other computersX Automated test equipment (ATE)X

Introduction 31.3 SpecificationsDigital I/O (DIO)X Numbers of Channel: 32 TTL compatible inputs and/or out-putsX Device: IDT 74FCT373X I/O Configurat

4 IntroductionTransfer CharacteristicX Mode: Bus Mastering DMA with Scatter/GatherX Data Transfers: 8/16/32-bit input or output (programmable)DMA Tra

Introduction 5X Power Consumption: PCI-7300A:Z +5 V @ 830 mA typical (onboard terminator off), 1.0 A typical (onboard terminator on)PCIe-7300A: Z +12

6 Introduction1.4 Software SupportADLINK provides versatile software drivers and packages for users’ different approach to built-up a system. We not

Introduction 7are free shipped with the board. You can install and use them without license. For detail information about DAQ-LVIEW PnP, please ref

8 Introduction

Installation 92 InstallationThis chapter describes how to install the cPCI/PCI/PCIe-7300A. At first, the contents in the package and unpacking inform

Copyright 2008 ADLINK TECHNOLOGY INC.All Rights Reserved. The information in this document is subject to change without prior notice in order to impro

10 Installation2.2 UnpackingYour cPCI/PCI/PCIe-7300A card contains sensitive electronic components that can be easily damaged by static electricity.T

Installation 112.4 cPCI/PCI/PCIe-7300A LayoutFigure 2-1: PCI-7300A Layout Diagram

12 InstallationFigure 2-2: cPCI-7300A Layout DiagramFigure 2-3: PCIe-7300A Layout Diagram167.65111.15

Installation 132.5 Hardware Installation OutlinePCI configurationThe cPCI/PCI/PCIe cards are equipped with plug and play PCI controller, it can reque

14 Installation2.6 Connector Pin AssignmentThe PCI/cPCI/PCIe-7300A comes equipped with one 100-pin SCSI type connector (CN1) located on the rear moun

Installation 1584 DITRIG CONTROL IDI TRIG – can be used to control the start of data acquisition in all DI modes.78…81 AUXDI3…0 DATA IAUX DI 3…0 – ca

16 InstallationFigure 2-4: CN1 Pin Assignment

Installation 172.7 Wiring and TerminationTransmission line effects and environment noise, particularly on clock and control lines, can lead to incor

18 Installation2.8 Termination Board SupportThe cPCI/PCI/PCIe-7300A can be connected with two termination boards: DIN-100S or DIN-502S. The functiona

Registers 193RegistersIn this chapter, the registers’ format of the cPCI/PCI/PCIe-7300A is described. This information is quite useful for the progra

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20 Registers3.1 I/O Port Base AddressThe registers of the cPCI/PCI/PCIe-7300A are shown in Table 3.1. The base address of these registers is also ass

Registers 21Legend:X DI_CSR: Digital input control & status registerX DO_SCR: Digital output control & status registerX AUX_DIO: Auxiliary di

22 Registers3.2 DI_CSR: DI Control & Status Register Digital input control and status checking is done by this register.Address: BASE + 00Attribu

Registers 23DI_EN (R/W) X 0: Disable digital inputsX 1: Enable digital inputsDI_FIFO_CLR (R/W) X 0: No effectX 1: Clear digital input FIFO. If both P

24 Registers3.3 DO_CSR: DO Control & Status RegisterDigital input control and status checking is done by this register.Address: BASE + 04Attribut

Registers 25X 0: start output data immediatelyX 1: delay output data until DOTRIG is actived PB_TERM_OFF (R/W) X 0: PORTB terminator ONX 1: PORTB ter

26 Registers3.4 Auxiliary Digital I/O RegisterAuxiliary 4-bit digital inputs and 4-bit digital outputsAddress: BASE + 08 Attribute: READ/WRITEData Fo

Registers 273.5 INT_CSR: Interrupt Control and Status Register The interrupt of cPCI/PCI/PCIe-7300A is controlled and status is checked through this

28 Registers3.6 DI_FIFO: DI FIFO direct access port The digital input FIFO data can be accessed through this port directly. Address: BASE + 0x10Attr

Registers 293.7 DO_FIFO: DO external data FIFO direct access port The digital output FIFO data can be accessed through this port directly. Address:

30 Registers3.8 FIFO_CR: FIFO almost empty/full register The register is used to control the FIFO programmable almost empty/full flag. Address: BASE

Registers 313.9 POL_CNTRL: Control Signal Polarity Control Register The register is used to control the control signals’ polarity. The control sign

32 Registers3.10 PLX PCI-9080 DMA Control RegistersThe registers of bus-mastering DMA as well as the control and status registers of PCI-bus interrup

Operation Theory 334 Operation TheoryThis chapter provides the detailed operation information for the cPCI/PCI/PCIe-7300A, including I/O configurati

34 Operation Theory4.1 I/O ConfigurationThe 32-bit I/O data path of PCI/cPCI/PCIe-7300A can be config-ured as 8-bit, 16-bit, or 32-bit, the possible

Operation Theory 354.2 Block DiagramFigure 4-1 shows the block diagram of the cPCI/PCI/PCIe-7300A, it includes the I/O registers, two 16K FIFOs, aux

36 Operation Theory4.3 Digital I/O Data FlowWhen applying digital input functions, the data will be sampled into the input FIFO periodically as we co

Operation Theory 374.4 Input FIFO and Output FIFODue to the data transfer rate between external devices and the cPCI/PCI/PCIe-7300A is independent f

38 Operation Theory4.5 Bus-mastering DMADigital I/O data transfer between cPCI/PCI/PCIe-7300A and PC’s system memory is through bus mastering DMA, wh

Operation Theory 39hard-disk rather than memory, the bottleneck would be the data transfer rate of the hard-disk driver.

iTable of ContentsList of Tables... ivList of Figures ...

40 Operation Theory4.6 Scatter/gather DMAThe PCI Bridge also supports the function of scatter/gather bus mastering DMA, which helps the users to tran

Operation Theory 414.7 Clocking ModeThe data input to or output from the FIFO is operated in a specific rate. The specific sampling rate or the pace

42 Operation Theorytion of DI-ACK. If the external device follows the rule, there would be no data lost due to FIFO overrun.3. Handshaking: For the d

Operation Theory 434.8 Starting ModeUsers can also control the starting mode of digital input and output by external signals (DITRIG and DOTRIG) wit

44 Operation Theory4.9 Active TerminatorFor cPCI/PCI/PCIe-7300A, it is important to terminate your cable properly to reduce or eliminate signal refle

Operation Theory 454.10 Digital Input Operation Mode4.10.1Digital Input DMA in Internal Clock ModeThere are three sources to trigger digital input i

46 Operation TheoryThe operation flow is show as below: Note: When the DMA function of digital input starts, the input data will be stored in the FI

Operation Theory 47than the on-board FIFO buffer time. The FIFO size is 16K sample, so it has 1.6 ms buffer time for 10MHz sampling rate if the FIFO

48 Operation TheoryThe operation flow is show as below: The followings are timing diagrams of the DI-REQ and the input data. The active edge of DI-RE

Operation Theory 49Figure 4-8: DIREQ as input data strobe (Falling Edge Active)Note: From the timing diagram of external clock mode, the maxi-mum f

ii 4 Operation Theory... 334.1 I/O Configuration...

50 Operation Theoryfer.The operations sequence of digital input with handshaking are listed:1. Define the input configuration to be 32-bit, 16-bit or

Operation Theory 51The following figure shows the timing requirement of the hand-shaking mode digital input operation.Figure 4-9: DIREQ & DIACK

52 Operation Theoryand remove the unnecessary processes in your applica-tion programs.3. When high-speed sampling frequency is applied, the larger bl

Operation Theory 534.11 Digital Output Operation Mode4.11.1 Digital Output DMA in Internal Clock ModeThere are three sources to trigger digital outp

54 Operation TheoryAs the data output in the internal clock mode, the DOREQ signal could be use as the output strobe to indicate the output operation

Operation Theory 55The operations sequence of digital output in handshaking mode are listed:1. Define the input configuration to be 32-bit, 16-bit o

56 Operation TheoryThe timing diagram of the DOREQ and DOACK in the DO hand-shaking mode is shown as follows:Figure 4-11: DOREQ & DOACK Handshaki

Operation Theory 57The operations sequence of digital output in burst handshaking mode are listed:1. Define the input configuration to be 32-bit, 16

58 Operation TheoryThe operation flow is show as below: Note: When the DMA function of digital output starts, the output data will transfer to the ou

Operation Theory 594.11.4 Pattern GeneratorThe digital data is output to the peripheral device periodically based on the clock signals occur at a co

iii5.18 _7300_DO_DMA_Start... 855.19 _7300_DO_DMA_Status ...

60 Operation Theory4.12 Auxiliary DIOThe cPCI/PCI/PCIe-7300A also includes four auxiliary digital inputs and four digital outputs, which can be appli

C/C++ Libraries 615 C/C++ LibrariesThis chapter describes the software library for operating this card. Only the functions in DOS library and Window

62 C/C++ Libraries5.1 Libraries InstallationPlease refer to the “Software Installation Guide” for the detail infor-mation about how to install the so

C/C++ Libraries 635.2 Programming GuideNaming ConventionThe functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver are using f

64 C/C++ Libraries5.3 _7300_Initial@ DescriptionA cPCI/PCI/PCIe-7300A card is initialized according to the card number. Because the cPCI/PCI/PCIe-730

C/C++ Libraries 65irq_no:system will give an available interrupt number to this card automatically.pci_master:TRUE: BIOS enabled PCI bus mastering

66 C/C++ Libraries5.4 _7300_Close@ DescriptionClose a previously initialized cPCI/PCI/PCIe-7300A card.@ SyntaxVisual C/C++ (Windows 95)int W_7300_Clo

C/C++ Libraries 675.5 _7300_Configure@ DescriptionSet the port DI/O configuration, terminator control, and control sig-nal polarity for the cPCI/PCI

68 C/C++ LibrariesPAON_PBOFF: PORTA terminator ON, PORTB terminator OFFPAON_PBON: PORTA terminator ON, PORTB terminator ONNote: term_cntrl is used to

C/C++ Libraries 695.6 _7300_DI_Mode@ DescriptionSet the clock mode and start mode for the cPCI/PCI/PCIe-7300A DI operation.@ SyntaxVisual C/C++ (Win

iv List of TablesList of TablesTable 2-1: Connector Pin Assignment ... 14Table 3-1: I/O Port Base Address ...

70 C/C++ Libraries5.7 _7300_DO_Mode@ DescriptionSet the clock mode and start mode for the cPCI/PCI/PCIe-7300A DO operation.@ SyntaxVisual C/C++ (Wind

C/C++ Libraries 71DO_WAIT_FIFO: delay output data until FIFO is not almost emptyDO_WAIT_BOTH: delay output data until DOTRIG is active and FIFO is n

72 C/C++ Libraries5.8 _7300_AUX_DI@ DescriptionRead data from auxiliary digital input port. You can get all 4 bits input data by using this function.

C/C++ Libraries 735.9 _7300_AUX_DI_Channel@ DescriptionRead data from auxiliary digital input channel. There are 4 digital input channels on the cPC

74 C/C++ Libraries5.10 _7300_AUX_DO@ DescriptionWrite data to auxiliary digital output port. There are 4 auxiliary dig-ital outputs on the cPCI/PCI/P

C/C++ Libraries 755.11 _7300_AUX_DO_Channel@ DescriptionWrite data to auxiliary digital output channel (bit). There are 4 aux-iliary digital output

76 C/C++ Libraries5.12 _7300_Alloc_DMA_Mem@ DescriptionContact Windows 95 system to allocate a memory for DMA trans-fer. This function is only availa

C/C++ Libraries 775.13 _7300_Free_DMA_Mem@ DescriptionDeallocate a system DMA memory under the Windows 95 envi-ronment. This function is only availa

78 C/C++ Libraries5.14 _7300_DI_DMA_Start@ Description The function will perform digital input by DMA data transfer.It will take place in the backgro

C/C++ Libraries 79transfers are always longwords, this is 2 million long-words (2^21).3. After the input sampling is started, the input data is stor

List of Figures vList of FiguresFigure 2-1: PCI-7300A Layout Diagram... 11Figure 2-2: cPCI-7300A Layout Diagram..

80 C/C++ LibrariesByVal clear_fifo As Long, ByVal disable_di As Long) As LongC/C++ (DOS)int _7300_DI_DMA_Start (int card_number, int mode, U32 *buffe

C/C++ Libraries 81disable_di:0: digital input operation still active after DMA trans-fer complete1: disable digital input operation immediately when

82 C/C++ Libraries5.15 _7300_DI_DMA_Status@ Description Since the _7300_DI_DMA_Start function is executed in back-ground, you can issue this function

C/C++ Libraries 835.16 _7300_DI_DMA_Abort@ Description This function is used to stop the DMA DI operation. After executing this function, the DMA tr

84 C/C++ Libraries5.17 _7300_GetOverrunStatus@ Description When you use _7300_DI_DMA_Start to input data, the input data is stored in the FIFO of PCI

C/C++ Libraries 855.18 _7300_DO_DMA_Start@ Description The function will perform digital output N times with DMA data transfer. It will takes place

86 C/C++ Libraries** This memory should be double-word alignmentcount:For non-chaining mode, this is the total number of digital output data in doubl

C/C++ Libraries 875.19 _7300_DO_DMA_Status@ Description Since the _7300_DO_DMA_Start function is executed in back-ground, you can issue the function

88 C/C++ Libraries5.20 _7300_DO_DMA_Abort@ Description This function is used to stop the DMA DO operation. After execut-ing this function, the _7300_

C/C++ Libraries 895.21 _7300_DO_PG_Start@ Description The function will perform pattern generation with the data stored in buff_ptr. It will takes p