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viii List of Figures

List of Figures

Figure 2-1: PCI-7300A Layout Diagram....................................... 9

Figure 2-2: cPCI-7300A Layout Diagram ................................... 10

Figure 2-3: CN1 Pin Assignment................................................ 14

Figure 4-1: Block diagram .......................................................... 32

Figure 4-2: Data flow of digital input........................................... 33

Figure 4-3: Data flow of digital output ........................................ 33

Figure 4-4: Maximum data throughput ....................................... 35

Figure 4-5: Scatter/gather DMA for digital output....................... 37

Figure 4-6: Timer configuration .................................................. 38

Figure 4-7: DIREQ as input data strobe (Rising Edge Active) ... 44

Figure 4-8: DIREQ as input data strobe (Falling Edge Active)... 45

Figure 4-9: DIREQ & DIACK Handshaking................................ 47

Figure 4-10: DOREQ as output data strobe................................. 50

Figure 4-11: DOREQ & DOACK Handshaking ............................ 52

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