Adlink DAQe-2006 Bedienungsanleitung PDF herunterladen (Seite 80)

68 Operation Theory

4.6 User-controllable Timing Signals

In order to meet the requirements for user-specific timing and

requirements for synchronizing multiple cards, the DAQ-/DAQe-/

PXI-2016/2010/2006/2005 card provides flexible user-controllable

timing signals to connect to external circuitry or additional cards.

The whole DAQ timing of the DAQ-/DAQe-/PXI-2016/2010/2006/

2005 card is composed of a bunch of counters and trigger signals

in the FPGA. These timing signals are related to the A/D, D/A con-

versions, and Timer/Counter applications. These timing signals

can be input to or output from the I/O connectors, SSI connector,

and the PXI bus. Therefore, the internal timing signals can be

used to control external devices or circuitry. Note that in other

models of DAQ-/DAQe-/PXI-2016/2010/2006/2005 card, the user-

controllable timing signals may vary. However, the SSI/PXI timing

signals remain the same for every DAQ-/DAQe-/PXI-2016/2010/

2006/2005 card.

We implemented signal multiplexers in the FPGA to individually

choose the desired timing signals for the DAQ operations, as

shown in the Figure 4-38

Figure 4-38: DAQ signals routing

You can utilize the flexible timing signals through our software

drivers, then simply and correctly connect the signals with the

DAQ-/DAQe-/PXI-2016/2010/2006/2005 cards. Here is the sum-

mary of the DAQ timing signals and the corresponding functional-

ities for DAQ-/DAQe-/PXI-2016/2010/2006/2005 card.

1 2 ... 75 76 77 78 79 80 81 82 83 84 85 ... 91 92

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Adlink DAQe-2006 Bedienungsanleitung Seite 80