Adlink DAQe-2502 Bedienungsanleitung Seite 41
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Operation Theory 31
4.2 D/A Conversion
The DAQ-/DAQe-/PXI-2502/2501 card offers flexible and versatile
analog output scheme to fit your complex field applications. In
order to take full advantages of the DAQ-/DAQe-/PXI-2502/2501
card, it is suggested that you carefully read this section.
Architecture
There are up to eight channels of 12-bit Digital-to-Analog Con-
verter (DAC) available in the DAQ-/DAQe-/PXI-2502/2501 card.
Four D/A channels are packed into one D/A group. The DAQ-/
DAQe-/PXI-2502 comes with two D/A groups, while the DAQ-/
DAQe-/PXI-2501 card has only one D/A group.
Figure 4-6: Block Diagram of D/A Group
(Group B of DAQ/DAQe-/PXI-2502 is identical to Group A shown above.)
Figure 4-6 shows the D/A block diagram. DAC are controlled
implicitly by CPLD and have their outputs updated only when digi-
tal codes for all enabled DA channels are ready and latched. This
ensures D/A conversions to be synchronized for each channel in
the same D/A group. You can use this property to perform multi-
channel waveform generation without any phase-lag.
- NuDAQ-2500 Series 1
- Getting service 3
- Using this manual 5
- 1.3 Conventions 6
- Table of Contents 7
- List of Tables 9
- List of Figures 10
- 1 Introduction 11
- 1.2 Applications 12
- 1.3 Specifications 13
- Analog Input (AI) 14
- Ω / 6 pF 14
- Analog Trigger (A.Trig) 15
- 6Introduction 16
- 1.4 Block Diagram 17
- 1.5 Software Support 18
- DAQ-LVIEW PnP: LabVIEW Driver 19
- D2K-OCX: ActiveX Controls 19
- 10 Introduction 20
- 2 Installation 21
- 2.2 Unpacking 22
- 2.3 Card Layout 23
- DAQ-2502/2501 24
- DPXI-2501/2502 25
- 2.4 PCI Configuration 26
- 3 Signal Connections 27
- Signal Connections 19 29
- 20 Signal Connections 30
- 4 Operation Theory 31
- AD Data Format 32
- Acquisition Modes 33
- Scan Timing and Procedure 34
- Operation Theory 25 35
- Figure 4-1: Scan Timing 35
- Trigger Modes 36
- Operation Theory 27 37
- ) * PSC_counter 37
- Figure 4-3: Delay Trigger 37
- 28 Operation Theory 38
- Operation Theory 29 39
- ADLINK All-in-One CD 40
- 4.2 D/A Conversion 41
- 32 Operation Theory 42
- Figure 4-7: FIFO Data Format 42
- Setting up the DACs 43
- Software Update 44
- Waveform Generation 45
- Waveform Generation Timing 46
- Operation Theory 37 47
- Operation Theory 39 49
- 40 Operation Theory 50
- Iterative Waveform Generation 51
- 42 Operation Theory 52
- Operation Theory 43 53
- Figure 4-14: Stop Mode I 53
- 44 Operation Theory 54
- Figure 4-15: Stop Mode II 54
- Figure 4-16: Stop Mode III 54
- Operation Theory 45 55
- 46 Operation Theory 56
- Operation Theory 47 57
- Figure 4-17: Mode1 Operation 57
- 48 Operation Theory 58
- Figure 4-18: Mode2 Operation 58
- Figure 4-19: Mode 3 Operation 58
- Operation Theory 49 59
- Figure 4-20: Mode4 Operation 59
- Figure 4-21: Mode5 Operation 59
- 50 Operation Theory 60
- Figure 4-22: Mode6 Operation 60
- Figure 4-23: Mode7 Operation 60
- Operation Theory 51 61
- Figure 4-24: Mode8 Operation 61
- 4.5 Trigger Sources 62
- 54 Operation Theory 64
- Operation Theory 55 65
- 4.6 Timing Signals 66
- Operation Theory 57 67
- 58 Operation Theory 68
- 5 Calibration 69
- 5.2 Auto-calibration 70
- Appendix 71
- Warranty Policy 73
- 64 Warranty Policy 74
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