Adlink nanoX-TC Bedienungsanleitung PDF herunterladen (Seite 17)

Page 17 Express-IA533 User’s Manual Page 17 Express-IA533 User’s Manual nanoX-TC User’s Manual Page 17

Row A

Signal Descriptions (cont’d)

Pin Si

nal Descri

tion T

ePU/PD Comment

A56 RSVD NC - -

A57 G ND Ground P WR - -

A58 P CIE _ T X3+ PCIe 3 TX+ (port 0 of CP U, occupied) O - DP - used for PC H E G20T

A59 P CIE

T X3- P CIe 3 TX-

ort 0 of CPU

occu

ied

)

O - DP - used for PCH E G20T

A60 GND(FIXE D) Ground P WR - -

A61 P CIE _ T X2+ P CIe 2 TX+ (

ort 3 of C P U) O - D P - -

A62 P CIE _ T X2- P C Ie 2 TX- (port 3 of CPU) O - DP - -

A63 GPI1 GP I1 or SDIO controller 0 data 1 IO-3.3 P U 10k 3.3V BIOS select

A64 P CIE _ T X1+ P CIe 1 TX+ (port 2 of CP U) O - DP - -

A65 P CIE

T X1- P CIe 1 TX-

ort 2 of CPU

)

O - DP - -

A66 G ND Ground P WR - -

A67 GPI2 GP I2 or SDIO controller 0 data 2 IO-3.3 P U 10k 3.3V BIOS select

A68 P CIE _ T X0+ P CIe 0 TX+ (port 1 of CP U) O - DP - -

A69 P CIE _ T X0- P CIe 0 TX- (

ort 1 of CPU) O - DP - -

A70 GND(FIXE D) Ground P WR - -

A71 L VDS _ A0+ LVDS Channel A O - DP - -

A72 LVDS_ A0- LVDS Channel A O - DP - -

A73 L VDS

A1+ LVDS Channel A O - DP - -

A74 LVDS_ A1- LVDS Channel A O - DP - -

A75 L VDS _ A2+ LVDS Channel A O - DP - -

A76 LVDS_ A2- LVDS Channel A O - DP - -

A77 LVDS _ VDD_ E N LVDS VDD Panel Power O-2,5 PD 10k -

A78 L VDS _ A3+ LVDS Channel A O - DP - -

A79 LVDS

A3- L VDS Channel A O - DP - -

A80 GND(FIXE D) Ground P WR - -

A81 LVDS _A_ CK+ LVDS Channel A Clock O - DP - -

A82 LVDS _A_ CK- L VDS Channel A Clock O - DP - -

A83 LVDS_ I2C _CK LVDS I2C Clock IO-3.3 PU 2.2k 3.3V -

A84 LVDS_I2C_DAT LVDS I2C Data IO-3.3 PU 2.2k 3.3V -

A85 GPI3 GP I3 or SDIO controller 0 data 3 IO-3.3 P U 10k 3.3V BIOS select

A86 RSVD NC - -

A87 RSVD NC - -

A88 PCIE_CLK_REF+ PCI Express Clock Reference O - DP - -

A89 PCIE_CLK_REF- PCI Ex

ress Clock Reference O - DP - -

A90 GND(FIXE D) Ground P WR - -

A91 S PI_ POWER P ower source for S PI devices on carrier P WR - -

A92 S P I_ MIS O Da ta in to Module from Ca rrier S P I I-3. 3 -

A93 GPO0 GP O0 or S DIO controller 0 clock O-3.3 PU 10k 3.3V BIOS select

A94 SPI_CLK Clock from Module to Carrier SPI O-3.3 -

A95 S PI_MOSI Data out from Module to Carrier SPI O-3.3 -

A96 TPM_PP (TPM) Physical Presence pin I-3.3 -

A97 TYP E 10

Rev 2.0 / T

e 10 indicator to carrier S TO PD 4.7k -

A98 SE R 0_TX S erial 0 port trans mitter O-5 -

A99 SE R 0_R X S erial 0

ort receiver I-5 -

A100 GND(FIXE D) Ground P WR - -

A101 S E R1_TX S erial 1 port transmitter / or CAN CAN_AX O-5 -

A102 S E R 1_RX S erial 1 port receiver / or CAN CAN_ RX I-5 -

A103 LID# ACPI type LID switch I-3.3 PU 4.7k 3.3V

A104 VCC_ 12V P ower 12V P WR - -

A105 VCC_ 12V P ower 12V P WR - -

A106 VCC_ 12V P ower 12V P WR - -

A107 VCC_ 12V P ower 12V P WR - -

A108 VCC_ 12V P ower 12V P WR - -

A109 VCC_ 12V P ower 12V P WR - -

A110 GND(FIXE D) Ground P WR - -

XXX Strikethrough pin names indicates that the signal is not supported on this module.

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 61 62

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