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Registers • 27

Write 1 to clear the trigger status:

0: no effect

1: clear trigger detect status

Clear SC_TC(Bit2) : Write 1 to clear

Write 1 to clear Scan Counter Terminal Count status

0: no effect

1: clear the SC_TC status

Clear ADOR(Bit1) : Write 1 to clear

Write 1 to clear the A/D Overrun Status

0: no effect

1: clear the A/D Overrun status

Clear ADOS(Bit0) : Write 1 to clear

Write 1 to clear the A/D Over Speed Status:

0: no effect

1: clear the A/D Over-Speed status

4.8 A/D & FIFO Status Register

Address:

BASE + 28

Attribute:

read

Data Format:

Bit 7 6 5 4 3 2 1 0

ACQ Full HFull Empty Trg_det SC_TC ADOR ADOS

Bit 15 14 13 12 11 10 9 8

--- --- --- --- --- --- --- ---

Bit 23 22 21 20 19 18 17 16

--- --- --- --- --- --- --- ---

Bit 31 30 29 28 27 26 25 24

--- --- --- --- --- --- --- ---

Table 11. A/D & FIFO Status Register

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 97 98

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