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Chapter 3 Hardware

CoreModule 435 Reference Manual 29

Gigabit Ethernet Interface

The Gigabit Ethernet solution originates from the 82541PI Gigabit Ethernet controller and consists of both

the Media Access Controller (MAC) and the Physical Layer (PHY) combined into a single component

solution. The Gigabit Ethernet controller is a 64-bit PCIe control unit that features enhanced scatter-gather

bus mastering capabilities, which enable the processor to perform high-speed data transfers over the internal

PCIe bus. The bus master capabilities enable the component to process high-level commands and perform

multiple operations, thereby off-loading communication tasks from the CPU. The Gigabit Ethernet interface

offers the following features:

• Full duplex or half duplex support at 10 Mbps, 100 Mbps, or 1000 Mbps

• In full duplex mode, the Ethernet controller adheres to the IEEE 802.3x Flow Control specification

• In half duplex mode, performance is enhanced by a proprietary collision reduction mechanism

• IEEE 802.3 compatible physical layer to wire transformer

• IEEE 802.3u Auto-Negotiation support

• Fast back-to-back transmission support with minimum interframe spacing (IFS)

• IEEE 802.3x auto-negotiation support for speed and duplex operation

• 3 kB transmit and 3 kB receive FIFOs (helps prevent data underflow and overflow)

• On-board magnetics (Ethernet isolation transformer)

Table 3-11 describes the pin signals of the Gigabit Ethernet header which consists of 10 right-angle pins,

two rows, odd/even (1,2) pin sequence, and 0.079" (2mm) pitch.

Note: The shaded table cells denote ground.

Table 3-11. Gigabit Ethernet Interface Pin Signals (J23)

Pin # Signal Description

GND Ground

GND

3 MDI0+ Media Dependent Interface 0 +/-

4MDI0-

5 MDI1+ Media Dependent Interface 1 +/-

6MDI1-

7 MDI2+ Media Dependent Interface 2 +/-

8MDI2-

9 MDI3+ Media Dependent Interface 3 +/-

10 MDI3-

NOTE The magnetics (isolation transformer, T1) for the Ethernet connector is included

on the CoreModule 435.

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