
Chapter 3 Hardware
30 Reference Manual CoreModule 920
• Supports DVD-Audio and Audio Return channel
• Provides one 19-pin, standard HDMI micro connector
PEG (PCI Express Graphics):
• Supports external high-performance PCI Express graphics cards
• Supports general-purpose PCI Express devices
• Supports theoretical bandwidth of up to 8GT/s
• Provides PCIe Gen3 compliance
Table 3-10 defines the signals of the VGA interface, which consists of 10 pins, 2 rows, odd/even, (1, 2) with
0.079" (2mm) pitch.
Note: The shaded table cells denote power or ground.
Table 3-11 lists the pin signals of the LVDS video header, which provides 20 pins, 2 rows, odd/even pin
sequence (1, 2) with 0.079" (2mm) pitch.
Table 3-10. VGA Interface Pin Signal Descriptions (J17)
Pin # Signal Description
1 VSYNC Vertical Sync – This signal is used for the digital vertical sync (polarity is
programmable) 2.5V output to the VGA display.
2 HSYNC Horizontal Sync – This signal is used for the digital horizontal sync
(polarity is programmable) or “sync interval” 2.5V output to the VGA
display
3 DDC-CLK Display Control Clock
4 RED Red – This is the Red analog output signal to the VGA display.
5 DDC-DATA Display Control Data
6 GREEN Green – This is the Green analog output signal to the VGA display.
7
VDD5V0 Power – This is the +5 volts +/- 5% power signal from the external power
interface.
8 BLUE Blue – This is the Blue analog output signal to the VGA display.
9
GND Ground
10
GND Ground
Table 3-11. LVDS Video Interface Pin Signals (J23)
Pin # Signal Description
1
+12V +12 volts for flat panel and backlight
2
VCC_LVDS_CONN JP3 determines LVDS voltage (+3.3V or +5V)
3
GND Ground
4
GND Ground
5 LVDSA_CLK_P LVDS A Clock Positive
6 LVDSA_CLK_N LVDS A Clock Negative
7 LVDSA_DAT3_P LVDS A DATA Positive Line 3
8 LVDSA_DAT3_N LVDS A DATA Negative Line 3
9 LVDSA_DAT2_P LVDS A DATA Positive Line 2
10 LVDSA_DAT2_N LVDS A DATA Negative Line 2
11 LVDSA_DAT1_P LVDS A DATA Positive Line 1
12 LVDSA_DAT1_N LVDS A DATA Negative Line 1
Kommentare zu diesen Handbüchern